The invention relates to a method for fabricating a deep trench capacitor for dynamic memory cells, in which a trench is etched into a semiconductor substrate. In the interior, i.e., below a collar region near the top surface of the substrate, there is provided a doping and a dielectric. Then, the trench which which includes the doping and dielectric is filled with a conductive material to form an inner electrode. The inner electrode and the dielectric are etched away within the collar region, and a collar is formed using a collar process, comprising a collar oxide deposition and etching back of the collar oxide on the substrate surface and in the trench as far as the inner electrode. Then, the inner electrode is completed by further steps of depositing and etching back conductive layers.
Complex integrated circuits of dynamic memory chips have integrated capacitor structures formed using one of three different designs,
planar metal-insulator-silicon, double-polysilicon or metal-insulator-metal capacitors arranged parallel to the semiconductor surface,
stacked, three-dimensionally patterned capacitors on the semiconductor surface, known as STCs (stacked capacitors) or
three-dimensionally patterned trench capacitors, known as DTCs (deep trench capacitors), which are recessed inside the semiconductor substrate.
In a known trench capacitor, a trench is etched into a semiconductor substrate. In the interior, i.e., below a collar region close to the top surface, the trench is provided with a doping and a dielectric along its surface. This doping is also referred to as plate doping.
In terms of process technology, the doping is produced by outdiffusion out of an As glass layer which has previously been applied to the trench surface in the region of the area which will subsequently act as a capacitor area. To achieve a required doping level, the As glass layer has to have a minimum thickness all the way down to the lower region of the trench. This presents difficulties for feature sizes of less than 130 nm, since the demands for a minimum thickness can no longer be satisfied on account of the high aspect ratio of the trench structure, which is greater than 50, and the fact that the deposition conformity of the As CVD process used to produce the As glass layer is far from ideal.
After the doping, the trench which has been prepared in this way is provided with a dielectric and is then filled with a conductive material as inner electrode, the inner electrode and the dielectric in the region close to the top side are etched back within a collar region, and are then provided with a collar by means of a collar process comprising a collar oxide deposition and etching back the collar oxide on the substrate surface and in the trench as far as the inner electrode. Then, the inner electrode is completed by further steps of depositing and etching back conductive layers.
To improve the storage properties of dynamic memory cells, there is a constant effort to achieve the highest possible capacitance in the capacitors. For this purpose, in the case of STCs, i.e., in the case of the stacked capacitors, it is known to increase the specific capacitance, i.e., the capacitance per unit area. The increase in the capacitance is brought about by increasing the surface area by conductive grains of polysilicon being applied to the base surface of the capacitors. These grains are also known as rugged poly or HSG (hemispherical silicon grains). A use of HSG beyond their application for STCs is not known.
For trench capacitors, there is a wide range of known measures for increasing the capacitance, among which the following are given below:
a relative increase in the trench cross section and therefore also in the size of the trench within the memory cell territory,
an increase in the depth of the trench, which has hitherto been the most important measure in capacitor scaling but presenting increasing technical difficulties with scaling of the trench cross section,
selecting a bottle-shaped cross section for the trench, known as a bottle shaped capacitor, but this presents increasing etching difficulties in view of the aim to achieve a short distance between the trenches,
a reduction in the thickness of the dielectric, but this is limited by incipient charge carrier tunneling,
use of dielectrics with a higher dielectric constant, a measure which has not to date gained widespread use on account of difficulties with depositing the material, with integration or with the leakage current characteristics,
an increase in the roughness of the (internal) trench surface by means of pore etching (mesopores), which it has not to date been possible to achieve on account of the tight tolerances imposed on the mesopores.
The invention is therefore based on the object of increasing the capacitance of trench capacitors while maintaining the conventional collar process.